Re: DRC has announced its newest FPGA that drops into AMD's Socket 940

c d saunter wrote:
> tomstdenis@gmail.com wrote:
>
> : Jan Panteltje wrote:
> : > http://www.dailytech.com/article.aspx?newsid=1920
>
> <snip>
>
> : 8x200Mhz only provides 400MB/sec traffic to the CPU so really this is
> : useful for tasks which either totally reside on the FPGA side of the
> : board or have really high latency (e.g. PK work).
>
> Sitting on the HT bus like that offers residence about as close as you can
> get to a mainstream CPU. Given the new HT3 stuff - faster and links
> possible over 1 meter - i.e. directly joining blades - I really like this
> aproach. Especially given the memory architecture that goes along with
> HT/Opterons. It's bringing mainstream CPUs and FPGAs back into the point
> to point multiple interconnect world of the TigerSHARCs and the old TI
> C40s.

HT links are not solely designed for speed. Latency is the key. 16
lanes of PCIe can compete just fine with a 16x16 1Ghz HT link in terms
of bandwidth.

Oddly enough the best tasks for this are things which don't return back
to back [e.g. raytrace a scene].

What this does open the door for though is for mixed architecture
systems. E.g. synthesize a MIPS core in the FPGA and map the DDR
controller on to it.

Then you have x86 and MIPS in the same system.

That'd be cool.

Tom
Received on Mon May 1 02:05:51 2006