Re: DRC has announced its newest FPGA that drops into AMD's Socket 940

tomstdenis@gmail.com wrote:

: HT links are not solely designed for speed. Latency is the key. 16
: lanes of PCIe can compete just fine with a 16x16 1Ghz HT link in terms
: of bandwidth.

: Oddly enough the best tasks for this are things which don't return back
: to back [e.g. raytrace a scene].

I wouldn't call that odd - a modern CPU hiding behind caches with long
pipelines is always going to struggle with low latency
back/forewards/back/forewards shared tasks with an FPGA/Clearspeed/xxx
- certainly interesting things happen with FPGA silicon and CPU
silicon coupled in a SOC or on an FPGA but the clock rates are far below a
dedicated CPU.

On the serial / parallel issue I have a leaning towards parallel for
simplicity when it comes to the FPGA code and latency, although serial has
benefits for physical complexity and routing. Also it feels like they
leap frog each other every few months in terms of bandwidth! The world is
squeezing itself down a thin pipe these days though...

: What this does open the door for though is for mixed architecture
: systems. E.g. synthesize a MIPS core in the FPGA and map the DDR
: controller on to it.

: Then you have x86 and MIPS in the same system.

: That'd be cool.

An awfull lot of cool things are on their way...
Received on Mon May 1 02:05:51 2006