Re: DRC has announced its newest FPGA that drops into AMD's Socket 940

c d saunter wrote:
> tomstdenis@gmail.com wrote:
>
> : Jan Panteltje wrote:
> : > http://www.dailytech.com/article.aspx?newsid=1920
>
> <snip>
>
> : 8x200Mhz only provides 400MB/sec traffic to the CPU so really this is
> : useful for tasks which either totally reside on the FPGA side of the
> : board or have really high latency (e.g. PK work).
>
> Sitting on the HT bus like that offers residence about as close as you can
> get to a mainstream CPU. Given the new HT3 stuff - faster and links
> possible over 1 meter - i.e. directly joining blades - I really like this
> aproach. Especially given the memory architecture that goes along with
> HT/Opterons. It's bringing mainstream CPUs and FPGAs back into the point
> to point multiple interconnect world of the TigerSHARCs and the old TI
> C40s.
>
> It feels a bit like a resurgence to the old British Transputer except with
> gate arrays mixing with CPUs on an equal footing in terms of connectivity.
>
> cds

Um yes it does look familiar doesn't it. If you go to the origins of HT
when it was called something else at AlphaWorks IIRC, the key people
had originally come from Inmos and had worked on the PLLs for the
Transputer and maybe those links too. The fellow is now a Fellow at AMD
after they bought them out. In a previous life, same people were at
Meiko and did their own routers used to stitch up T800s then later
several other cpus ultimately leading to the Alpha platform after Meiko
went belly up.

When I first heard Xilinx was taking a HT license, which seems a long
time ago now, I wondered when this would happen.

When I first saw the early marketing for the Hammer with 1,2,3,4 of
these HT links and the memory channel too, I could only say out loud,
looks & smells like a Transputer to me with 20yrs development but it
isn't really, it doesn't have the process scheduler or any real support
for programming concurrently per occam, just links. But when I see the
product today with a huge price premium on the no of HT links, I am
dissapointed, one Opteron with 1 link is cheap enough, add more links,
the cost goes way up as it looks more and more like a server platform.
The no of Links on the Transputer was always an issue back then, 4 is a
minimum.

The socket module though looks a bit like SFF TRAM module but the multi
socket Opteron boards are not really TRAM carriers that can be
populated with general purpose computing modules on a grid. Perhaps
that will come back again but probably with more modest links.

I have been suggesting a Transputer resurgence for some time by
building an FPGA Processor Element hooked up with a specialized MMU
that shares the available memory bandwidth of RLDRAM amongst many PEs
using latency hiding Multithreading to make the PEs not appear to have
any memory wall. By distributing n.PE+MMUs into the fabric, one can
then add algorithm specific extentions or coprocessors to each and copy
the node systolic fashion over the array. Each PE only uses only 1
BRam, so quite a few PEs would fit. The Transputer is really now
defined by all the good stuff that goes into the MMU rather than the
PEs. There is a paper on it at wotug.org for anyone interested.

When you build algorithms in FPGA around arrays of customizeable PEs I
think some of the reasons for having an Opteron in the system may
become moot, put the cpus into the FPGA as many copies as you can get
since all the real bandwidth is in/out of all the Blockrams, not the
more limited I/O pins.

I will have to look more into HT3 though.

John Jakson
transputer guy
Received on Mon May 1 02:05:54 2006